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draft dual-mode wpc/pma 5 watt wireless power receiver ic p9028ac product datasheet revision 1.0.3 1 ? 2015 integrated device technology, inc. features ? single chip receiver (rx) solution ? wpc v1.1.2 compliant ? pma v1, v3 pre-release compatible with options ? advanced wpc v1.1.2 foreign object detection (fod) ? programmable fod setting via external resistor and i 2 c registers ? programmable current limit via external resistor ? integrated full-bridge synchronous rectifier ? integrated 5v @ 1a ldo regulator output ? closed-loop power transfer control between tx and rx ? i 2 c interface provides vrec t, iout and switching frequency values ? open-drain led indicator output ? over-temperature/voltage /current protection applications ? wpc-compliant and pma-compatible wireless chargers for mobile applications. ? cellular mobile phones ? tablets, dsc, dvc and handhelds introduction the p9028ac is an integrated single-chip, dual-mode wpc v1.1.2-compliant and pma v1.0-compatible, wireless power receiver ic with advanced wpc v1.1.2 foreign object detection (fod). the device operates with an ac power signal from a resonant tank and converts it into a regulated 5v output voltage, which can be used to supply power to a mobile application. it includes a high efficiency synchronous full bridge rectifier and 5v tracking ldo output stage. the p9028ac dual-mode operation automatically detects the transmitter type and initiates either wpc or pma ac modulation communication protocols with optimal efficiency. the device includes the control circuit required to modulate the load to transmit wpc-compliant or pma-compatible message packets to the base station. it uses minimal external components to reduce overall solution area. the p9028ac employs advanced programmable wpc fod techniques to detect foreign metallic objects placed on the transmitter base station derived from a transmitted and received power transfer algorithm. the p9028ac is available in a 36 ball 3mm x 3mm wlcsp or 32 pin 5mm x 5mm tqfn package. typical application circuit packages: wlcsp-36 6x6 balls (3.06mm x 2.9mm) (see page 33) tqfn-32 5x5mm (see page 35) ordering information: (see page 38)
p9028ac product datasheet revision 1.0.3 2 ? 2015 integrated device technology, inc. simplified application diagram figure 1. simplified applications schematic.
p9028ac product datasheet revision 1.0.3 3 ? 2015 integrated device technology, inc. absolute maximum ratings these absolute maximum ratings are stress ratings only. stresses greater than those listed below (table 1 and table 2) may cau se permanent damage to the device. functional operation of the p9028ac at absolute maximum ratings is not implied. application of the absolute ma ximum rating conditions affects device reliability. table 1. absolute maximum ratings summary. description value units ac1, ac2, vrect, acm1, acm2, clamp1, clamp2 -0.3 to 20 v bst1, bst2 -0.3 to (ac1, ac2 + 6) v en , stat , scl, sda, out, sns, teop , rlim, cs100, fod1, fod2, vdd -0.3 to 6 v pgnd, pgnd1, pgnd2, agnd -0.3 to 0.3 v output current out 1.5 a input current ac1, ac2 2 a rms table 2. package thermal information. 1,2,3,4 symbol description tqfn rating wlcsp rating (7 thermal vias) units ? ja thermal resistance junction to ambient 35 70 ? c/w ? jc thermal resistance junction to case 29.6 0.9 ? c/w ? jb thermal resistance junction to board 2.4 47.3 ? c/w t j operating junction temperature 0 to +125 0 to +125 ? c t a operating ambient temperature 0 to +85 0 to +85 ? c t stg storage temperature -55 to +150 -55 to +150 ? c t lead maximum soldering temperature (at leads, 10s) 300 300 ? c note 1: the maximum power dissipation is p d(max) = (t j(max) - t a ) / ja where t j(max) is 125c. exceeding the maximum allowable power dissipation will result in excessive die temperature, and the device will enter thermal shutdown. note 2: this thermal rating was calculated on jedec 51 standard 4-layer board with dimensions 3? x 4.5? in still air conditions. note 3: actual thermal resistance is affected by pcb size, solder joint quality, layer count, copper thickness, air flow, altitude, and other unlisted variables. note 4: for the nbg32 package, connecting the 5 mm x 5 mm ep to internal/external ground planes with a 5x5 matrix of pcb plated-through -hole (pth) vias, from top to bottom sides of the pcb, is recommended for improving the overall thermal performance. for the wlcsp (awg36) package, connecting the 7 thermal balls to internal/external ground planes from top to bottom sides of the pcb, is recommended for improving the ov erall thermal performance. table 3. esd information. test model pins rating units hbm all 1500 v cdm all 500 v
p9028ac product datasheet revision 1.0.3 4 ? 2015 integrated device technology, inc. electrical specification table v rect =6v, c out =1uf, c vrect =20uf, v en =0v, t a = 0c to 85 ? c, unless otherwise noted. typical values are at 25c, unless otherwise noted. table 4. device characteristics. symbol description conditions min typ max units under-voltage lock-out v uvlo under-voltage lockout rising voltage on vrect 2.3 2.5 2.7 v v uvlo-hys uvlo hysteresis 50 mv over-voltage protection v ovp over-voltage vrect rising voltage on vrect 12.8 13.3 13.8 v v ovp-hys over-voltage hysteresis 1.5 v power supply current i rect quiescent current i out = 0ma, with internal load 14 16 18 ma i out = 0ma, no internal load 2 3 4 ma low-drop-out regulato r i lim output current limit out r lim =30k ? 1.15 1.6 1.95 a r lim <25k ? (note 1) 2.0 v out regulated output voltage out i out = 0ma to 1000ma 5.04 5.3 5.56 v vdd voltage (for internal supply use only) v dd_int internal supply voltage i vdd = 100 ? 4.44 4.54 4.64 v thermal shutdown t shd thermal shutdown threshold temperature rising 150 c temperature falling 130 c digital input and output characteristics v il logic level input low en , cs100, teop 0.4 v v ih logic level input high en , cs100, teop 1.3 v v ol open drain voltage stat , int i stat = 4ma 400 mv r pd pull-down resistance en , cs100 200 k ? teop 1000 switch on-resistance r dson acm1, acm2 switches 150ma 1600 m ? clamp1, clamp2 switches 400 475 680 m ? rectifier bridge switches 60 110 180 m ?
p9028ac product datasheet revision 1.0.3 5 ? 2015 integrated device technology, inc. electrical specification table v rect =6v, c out =1uf, c vrect =20uf, v en =0v, t a = 0c to 85 ? c, unless otherwise noted. typical values are at 25c, unless otherwise noted. table 4. device characteristics (continued). symbol description conditions min typ max units scl, sda (i 2 c interface) f scl clock frequency 0 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t hd,sta hold time (repeated) for start condition 0.6 s t su:sta set-up time for repeated start condition 0.6 s t su:dat data setup time 100 ns t hd:dat data hold time 0.9 s t su:sto setup time for stop condition 0.6 s t buf bus free time between stop and start condition 1.3 s t r rise time of both sda and scl signals (note 1,2) 20 + 0.1 c b 300 ns t f fall time of both sda and scl signals (note 1,2) 20 + 0.1 c b 300 ns t sp spike pulse widths suppressed by input filter (note 1,2) 0 50 ns c b capacitive lo ad for each bus line (note 1,2) 400 pf c bin scl, sda input capacitance (note 1,2) 60 pf v il input threshold low 0.4 v v ih input threshold high 1.4 v i i input leakage current -1.0 1.0 a note 1: guaranteed by design. not 100% tested in production. note 2: guaranteed by design/simulation data.
p9028ac product datasheet revision 1.0.3 6 ? 2015 integrated device technology, inc. typical performance characteristics typical performance characteristics: system efficiency versus rx output power en = reset = 0, ta = 25 o c 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 00.511.522.533.544.55 efficiency ? (%) output ? power ? (w) p9028ac ? system ? efficiency ? (%) ? vs. ? output ? power ? (w) from ? idtp9235 ? (wpc) ? or ? pma ? tx ? (1mm ? space) idtp9235 pma ? figure 2. p9028ac wpc and pma system efficiency.
p9028ac product datasheet revision 1.0.3 7 ? 2015 integrated device technology, inc. figure 3. p9028ac rx startup-to-out waveforms from idtp9235 tx, i out =0a, ch1=vrect, ch2=v out , ch3=rx coil current, ch4=vdd. figure 4. p9028ac rx startup-to-out waveforms from idtp9235 tx, i out =1a, ch1=vrect, ch2= v out , ch3=rx coil current, ch4=vdd.
p9028ac product datasheet revision 1.0.3 8 ? 2015 integrated device technology, inc. figure 5. p9028ac rx startup-to-out waveforms from pma tx, i out =0a, ch1= v out , ch2= vrect, ch3= vdd, ch4= rx coil current. figure 6. p9028ac rx startup-to-out waveforms from pma tx, i out =0a, ch1= v out , ch2= vrect, ch3= vdd, ch4= rx coil current.
p9028ac product datasheet revision 1.0.3 9 ? 2015 integrated device technology, inc. pin configuration & description figure 7. p9028ac wlcsp pin configuration (top view).
p9028ac product datasheet revision 1.0.3 10 ? 2015 integrated device technology, inc. table 5. wlcsp pin descriptions. pin # name type description a1 chg_end/cs100 i active-high input pin. default setting is a charge-end active-high input from an external battery charger to terminate power transfer. alternatively, a charge-status active high input wh ich will send a wpc charge status packet with value 100 (100% charge). in pma mode, an end of charge (eoc) command will be sent. this pin has an internal pull down resistor. a2 out_a2 o 5v ldo output. a 0.1 f ceramic capacitor and a 1 f to 10 f ceramic capacitor must be connected between this pin and ground. a3 out_a3 a4 en i active-low enable pin. if this pin is pulled high, the chip will send a wpc eop packet with code 0x04 (over-voltage code) or a pma eoc signal. this pin has an internal pull down resistor. a5 clamp2_a5 i ac clamp input 2. a6 clamp2_a6 b1 vrect_b1 o output of the full-wave rectifier. b2 vrect_b2 b3 rlim i current-limit resistor. a resistor connected between this pin and ground sets the current limit of the 5v ldo. b4 teop i active-high over-temperature input pin. if this pin is pulled high, the chip will send a wpc eop packet with code 0x03 (over-temperature code) or a pma eoc signal. this pin has an internal pull down resistor. b5 pgnd2_b5 - power ground for the ac clamp fets. b6 pgnd2_b6 c1 ac1_c1 i ac1 input to the internal full-wave rectifier. c2 ac1_c2 c3 nc1 nc not internally connected. this pin may be connected to ground to improve thermal performance or to other pins to facilitate routing. c4 fod2 i foreign object detection 2 offset adjustment. c5 clamp1_c5 i ac clamp input 1. c6 clamp1_c6 d1 pgnd_d1 - power ground for the full-wave rectifier. d2 pgnd_d2 d3 dnc1 dnc do not connect to this pin, it is internally connected. this pin must be left floating. d4 acm1 i ac modulation input 1. d5 ac2_d5 i ac2 input to the internal full-wave rectifier. d6 ac2_d6 e1 bst2 o bootstrap output for high-side rectifier fet 2. e2 bst1 o bootstrap output for high-side rectifier fet 1. e3 dnc2 dnc internally connected. do not connect to this pin. this pin must be left floating. e4 scl i i 2 c clock port. if not used, connect to ground. e5 acm2 i ac modulation input 2. e6 pgnd1 - power ground for modulation fets. f1 int o interrupt output. open drain output pin. a low condition indicates that an oc, ov, or ot event has occurred. f2 stat o status output (stat . open drain output pin. a low condition indicates that power is being transferred. f3 vdd o internal voltage supply. connect a 1uf to 10uf capacitor between this pin and ground. must be left unloaded. f4 agnd - analog ground connection. f5 sda i/o i 2 c data port. if not used, connect to ground. f6 fod1 i foreign object detection 1 to select internal fod1 settings.
p9028ac product datasheet revision 1.0.3 11 ? 2015 integrated device technology, inc. pin configuration & description (continued) 1 2 3 4 5 6 7 11 12 13 14 15 16 30 29 28 27 26 25 8 23 22 21 20 19 18 17 24 int dnc1 dnc2 bst2 bst1 ac1 vrect rlim nc4 acm2 pgnd1 acm1 fod2 clamp1 pgnd2 clamp2 ac2 vdd agnd scl sda fod1 nc1 out nc2 en teop nc3 32 31 stat pgnd 9 10 sns chg_end/cs100 ep figure 8. p9028ac tqfn32 5mm x 5mm pin configuration (top view).
p9028ac product datasheet revision 1.0.3 12 ? 2015 integrated device technology, inc. table 6. tqfn pin descriptions. pin # name type description 1 int o interrupt output. open drain output pin. a low condition indicates that an oc, ov, or ot event has occurred. 2 dnc1 dnc do not connect to this pin, it is internally connected. this pin must be left floating. 3 dnc2 dnc do not connect to this pin, it is internally connected. this pin must be left floating. 4 bst2 o bootstrap output for high-side rectifier fet 2. 5 bst1 o bootstrap output for high-side rectifier fet 1. 6 ac1 i ac1 input to the internal full-wave rectifier. 7 vrect o output of the full-wave rectifier. 8 rlim i current-limit resistor. a resistor connec ted between this pin and ground sets the current limit of the 5v ldo. 9 sns i ldo output sense pin. connect to the out pin (tqfn only). 10 chg_end/cs100 i active-high input pin. default setting is a charge-end active-high input from an external battery charger to terminate power transfer. alternatively, a charge- status active high input which will send a wpc charge status packet with value 100 (100% charge). in pma mode, an end of charge (eoc) command will be sent. this pin has an internal pull down resistor. 11 nc1 nc not internally connected. this pin may be connected to others to facilitate routing or to improve thermal performance. 12 out o 5v ldo output. a 1 f ceramic capacitor must be connected between this pin and ground. 13 nc2 nc not internally connected. this pin may be connected to others to facilitate routing or to improve thermal performance. 14 en i active-low enable pin. the chip is suspended and placed in low-current (sleep) mode when pulled high. this pin is pulled low inside the chip. 15 teop i active-high over-temperature input pin. if th is pin is pulled high, the chip will send a wpc eop packet with code 0x03 (over-temperature code) or a pma eoc signal. this pin has an internal pull down resistor. 16 nc3 nc not internally connected. this pin may be connected to others to facilitate routing or to improve thermal performance. 17 clamp2 i ac clamp input 2. 18 pgnd2 - power ground for the ac clamp fets. 19 clamp1 i ac clamp input 1. 20 fod2 i fod2 adjustment 21 acm1 i ac modulation input 1. 22 pgnd1 - power ground for the full-wave rectifier. 23 acm2 i ac modulation input 2. 24 nc4 nc not internally connected. this pin may be connected to others to facilitate routing or to improve thermal performance. 25 fod1 i select fod settings 26 sda i/o i 2 c data port. if not used, connect to ground. 27 scl i i 2 c clock port. if not used, connect to ground. 28 agnd - analog ground connection. 29 vdd o internal voltage supply. connect a 1uf to 10ufcapacitor between this pin and ground. must be left unloaded.
p9028ac product datasheet revision 1.0.3 13 ? 2015 integrated device technology, inc. table 6. tqfn pin descriptions (continued). pin # name type description 30 ac2 i ac2 input to the internal full-wave rectifier. 31 pgnd - power ground for the full-wave rectifier. 32 stat o status output. a low condition indi cates that power is being transferred. ep exposed paddle - exposed pad for thermal
p9028ac product datasheet revision 1.0.3 14 ? 2015 integrated device technology, inc. functional block diagram pgnd driver & control peripherals stat i c scl sda gnd otp + digital multi channel adc with analog mux and digital control out vrect ldo5v control ac1 ac2 acm1 acm2 clamp1 clamp2 bst1 bst2 ac modulation and overvoltage protection gnd en internal ldo gnd 4.5v rlim current limit control eop control teop 2 cs100 fod1 fod2 vdd interrupt control int vin-uvlo figure 9. simplified internal block diagram.
p9028ac product datasheet revision 1.0.3 15 ? 2015 integrated device technology, inc. description of the wireless power charging system a wireless power charging system has a base station with one or more transmitters that make power available via dc-to-ac inverter(s) and transmit the power over a strongly-coupled inductor pair to a receiver in a mobile device. a wpc 1 transmitter may be a free-positioning or magnetically-guided type. pma 2 supports only the magnetically-guided configuration. a free-positioning type of transmitter has one coil or an array of coils that gives limited spatial freedom to the end-user, whereas a magnetically-guided type of transmitter helps the end-user align the receiver to the transmitter with a magnetic attraction. the amount of power transferred to the mobile device is controlled by the receiver. the receiver sends communication packets to the transmitter to increase power, decrease power, or maintain the power level. the bit rate for rx-to-tx communication link is 2-kbps for wpc compliant receivers and variable for pma compatible receivers. the communication is purely digital and communication 1?s and 0?s ride on top of the power link that exists between the two coils. theory of operation the p9028ac is a highly-integrated wireless power receiver ic for mobile devices. the device can transfer up to 5w from a wireless transmi tter to a load (e.g., a battery charger) in either wpc or pma (dual-mode) using near- field magnetic induction. dual-mode operation is achieved using a single rx coil with fixed inductance for both wpc and pma ac modulation for maximum efficiency. note 1 - refer to the wpc specification at http://www.wirelesspow erconsortium.com/ for the most current information. note 2 ? pma members can download the most current pma receiver interoperability specification at http://www.powermatters.org . overview the simplified internal block diagram of the p9028ac is shown in figure 9. an external inductor and capacitor transfers energy from the transmitter's coil through the p9028ac's ac1 and ac2 pins to be full-wave-rectified and stored on a capacitor connected to vrect. until the voltage across the capacitor exceeds the threshold of the vin_uvlo block, the rectific ation is performed by the body diodes of the synchronous full bridge rectifier fets. after the internal biasing circuit is enabled, the driver and control block operates the mosfet switches in the rectifier for increased efficiency. an internal adc monitors the voltage at vrect and the load current, the p9028ac sends instructions to the wireless power transmitter to increase or decrease the amount of power transferred or to terminate power transmission based on these readings. the voltage at the output of the 5v low- drop-out regulator and the internal temperature are also monitored to ensure proper operation. power control the voltage at vrect and the current through the rectifier are sampled periodically and digitized by the adc. the digital equivalents of the voltage and current are supplied to the internal control logic, which decides whether the loading conditions on vrect indicate that a change in the operating point is required. if the load is heavy enough to bring the voltage at vrect below its target, the transmitter is instructed to move its frequency lower, closer to resonance. if the voltage at vrect is higher than its target, the transmitter is instructed to increase its frequency. to maximize efficiency, the voltage at vrect is programmed to decrease as the ldo?s load current increases. wpc mode characteristics startup when a mobile device containing the p9028ac is placed on a wpc ?qi? charging pad, it responds to the transmitter?s ?ping? signal by rectifying the ac power from the transmitter and storing it on a capacitor connected to vrect. during the ?ping? phase, the rectifier provides about 5v at the vrect pin. an internal capacitor-less linear voltage regulator provides the supply voltage for the digital section to enable wpc communication. to increase the reliability of the communication, an internal load of about 15ma is connected to vrect until the external load is large enough to support communication.
p9028ac product datasheet revision 1.0.3 16 ? 2015 integrated device technology, inc. the control loop of the p9028ac adjusts the rectifier voltage to 7v by sending error packets to the transmitter before it enables the 5v ldo. the ldo is enabled when the power transfer mode is initiated and the voltage at vrect, the output of the full- wave synchronous rectifier, is 7v. the enable pin of the p9028ac can be asserted to shut down the ldo and send an ?end power transfer? communication packet to the transmitter. power transfer once the ?identification and configuration? phase is completed, the transmitter in itiates the power transfer mode. the p9028ac control circuit measures the rectifier voltage and sends error packets to the transmitter to adjust the rectifier voltage to the level required to maximize the efficiency of the linear regulator. synchronous rectifier the efficiency of the full-bridge rectifier in the p9028ac is increased by implementing it as a synchronous rectifier. the rectifier comprises four self-driven switches that work in a full synchronous mode of operation when the load is higher than 300 ma. below that threshold, the rectifier works in half-synchronous rectification mode. at power-up, when the voltage is below the uvlo threshold, the rectifier works by using the body diodes associated with the nmos transistors. charge pumps are used to drive the high-side nmos switches. advanced foreign object detection (fod) wpc mode when metallic objects are exposed to an alternating magnetic field, eddy currents cause such objects to heat up. examples of parasitic metal objects as such are coins, keys, paperclips, etc. the amount of heating depends on the amplitude and frequency of the magnetic field coupled, as well as on the characteristics of the object such as its resistivity, size, and shape. in a wireless power transfer system, the heating manifests itself as a power loss, and therefore a reduced power transfer efficiency. moreover, if no appropriate measures are taken, the heating could lead to unsafe situations if the objects reach high temperatures. wpc-compliant power transmitters and receivers need to also compensate for the power loss due to parasitic metals?i.e. metals that are neither part of the power transmitter, nor of the power receiver, but which dissipate power from magnetic field coupling during power transfer. the power transmitter uses both an input power and received power method to detect susceptible metallic objects near the interface surface. this method relies on analog ping and does not involve waking up the power receiver and starting digital communications. typically zero or more analog pings precede digital ping ing, which the power transmitter executes in an attempt to communicate with a possible receiver client device. the p9028ac employs advanced fod techniques to detect foreign objects placed on the transmitter base station. the fod algorithm includes values that are programmable through either the i 2 c interface or otp (one time programmable) bits. programmability is necessary so that the fod settings can be optimized to match the power transfer characteristics of each particular wpc system to include the power losses of the tx and rx coils, battery, shielding and case materials under no load to full load conditions. the values are based on the comparison of the received power against a reference power curve so that any foreign object can be sensed when the received power is different than the expected system power. the i 2 c interface fod option has 1 volatile setting that can accommodate the power transfer characteristics of one system . the otp option has up to 10 non-volatile value settings for up to ten different systems. the 10 programmed otp settings are externally selected through the fod1 setting resistor value (see figure 16 and 17) which selects the settings chosen for the particular system. a further enhancement is selected by the fod2 offset resistor which adds a -300 to +300mw power offset to the values selected by the fod1 resistor. there are three available options to set the advanced fod programming and testing: option 1: idt completes all the fod system tests and programming. option 2: idt completes the programming only with information provided by customer. option 3: the customer performs the fod system tests and programming. please contact idt for application note #814a which contains a detailed description of the advanced fod programming and options available.
p9028ac product datasheet revision 1.0.3 17 ? 2015 integrated device technology, inc. overvoltage protection in the event that the input voltage increases above 15v, the control loop disables the ldo, sends error packets to the transmitter in an attempt to bring the rectifier voltage below 7v, and clamps the input pins. if the voltage at vrect exceeds v ovp , two internal fets turn on to clamp the vrect voltage. this is accomplished through loading the receiver resonant tank with extra capacitance shorted to ground through the above mentioned internal fets. this changes the parallel resonance of the tank circuit which causes the tx to rx gain to decrease dramatically. the clamp is released when the vrect voltage falls below the v ovp hysteresis level. vrect must not be directly loaded. overcurrent protection and thermal shutdown the p9028ac employs over-current and thermal protection by sending an end of power packet to the transmitter when the output current reaches the current limit level or the die temp erature exceeds the thermal shutdown level. the ldo output is also disabled during these conditions. the current limit level is programmable with an external resistor: ? 45000 for any value of r lim below 25k ? , the output current is limited to 2a. rlim is not recommended to be set higher than 60k ohms rectifier and vrect level once vrect powers up to greater than 7v for wpc mode and 5.6v for pma mode, the full-bridge rectifier switches to half synchronous or full synchronous mode (depending on the loading conditions) to efficiently transfer energy from the transmitter to vrect. the control loop of the idtp9028ac maintains the rectifier voltage between 5v and 7v, depending upon the output current (i out ). the r lim resistor sets both the current limit (i lim ) and the vrect steps based on i set which is a reference current used to partition the i out load range into 4 regions, each with a vrect target for efficiency and transient optimization. i set is equal to: ? 38000 table 7. vrect target range. vrect i out 7v i out < 10% of i set 6.3v 10% of i set < i out < 20% of i set 5.5v 20% of i set < i out < 40% of i set 5.45v 40% of i set < i out status output the stat output goes low when the power transfer is established. interrupt output the int output goes low to indicate that an over-current, over-voltage or over-temperature event has occured. see electrical specifications for threshold levels. enable input if the particular application requires the p9028ac to be disabled, this can be accomplished with the en pin. when the en pin is pulled high, the device is suspended and placed in low current (sleep) mode. if pulled low or floating, the device is active. teop input in addition to the en input, the p9028ac can also be disabled with the teop pin. when the teop pin is pulled high, the chip will send an eop packet with code 0x03 (over-temperature code) . chg_end/cs100 input this pin has two functions. the charge-end default function will terminate power transfer when pulled high from an external battery charger. if the pin is set in charge-status mode, the device will send a wpc charge status packet with value 100 (100% charge) indicating a fully charged battery. in pma mode, an end of charge (eoc) command will be sent . ldo the p9028ac has one ldo, the 5 vout ldo that is powered by vrect. the ldo in turn supplies power to the system and/or charging circuitry. modulation/communication receiver-to-transmitter communication is accomplished by modulating the load seen by the receiver's inductor. to the transmitter, this appears as an impedance change, which results in measurable variations of the transmitter?s output waveform. modulation is done with ac modulation,
p9028ac product datasheet revision 1.0.3 18 ? 2015 integrated device technology, inc. using internal switches to connect external capacitors from ac1 and ac2 to ground the communication protocol is covered in the next section. wpc mode communication the p9028ac communicates with the base via communication packets. each communication packet has the following structure: preamble header message checksum figure 10. communication packet structure. according to the wpc specification, the power receiver communicates with the power transmitter using backscatter modulation. the load seen by the power transmitter?s inductor is modulated on the receiver side to send packets. the power transmitter detects this as a modulation of coil current/voltage to receive packets. bit encoding scheme as required by the wpc, the p9028ac uses a differential bi-phase encoding scheme to modulate data bits onto the power signal. a clock frequency of 2khz is used for this purpose. a logic one bit is encoded using two narrow transitions, whereas a logic zero bit is encoded using two wider transitions as shown below: figure 11. bit encoding scheme. each byte in the communication packet comprises 11bits in an asynchronous serial format, as shown below: figure 12. byte encoding scheme. each byte has a start bit, 8 data bits, a parity bit, and a single stop bit. system feedback control the p9028ac is fully compatible with wpc specification rev. 1.1 and has all necessary circuitry to communicate with the base station via wpc-compliant communication packets. the overall wpc-compliant system behavior between the transmitter and receiver follows the state machine below: figure 13. wpc system feedback control. the p9028ac goes through four phases: selection, ping, identification & configuration, and power transfer. selection in this phase, the p9028ac senses the incoming power from the base station and proceeds to the ping state. it monitors the rectified voltage, and when the voltage is above the v rect,uvlo threshold, the p9028ac wakes up its digital electronics and prepares to communicate with the base station. if the p9028ac does not proceed to ping , then it does not transmit any communication packets. ping in this phase, the p9028ac transmits a signal strength packet as the first communication packet to instruct the base to keep the power signal on. after sending the signal strength packet, the p9028ac proceeds to the identification and configuration phase. if, instead, the p9028ac sends end of power packets, then it remains in the ping phase. in this phase, the p9028ac sends the following packets: ? signal strength packet ? end of power packet
p9028ac product datasheet revision 1.0.3 19 ? 2015 integrated device technology, inc. identification and configuration (id & config) in this phase, the p9028ac may send the following packets: ? identification packet ? configuration packet after sending the configuration packet, the p9028ac proceeds to the power transfer phase. power transfer in this phase, the p9028ac controls the power transfer from the power transmitter by means of the following control data packets: ? control error packets ? rectified power packet ? end power transfer packet modulation the p9028ac is compatible with wpc v1.1 and pma v and v3 coils. each receiver coil type has a unique inductance value. as such, a unique resonant capacitor (c s ) is used for a given type of receiver coil. the modulation capacitors are shown in figure 14. dual-mode operates with a single lc tank rx coil and ac modulation for maximum efficiency. (c mode1 , c mod2 ) figure 14. modulation components. consult the factory for assistance with configuring a system with a specific coil type.
p9028ac product datasheet revision 1.0.3 20 ? 2015 integrated device technology, inc. pma mode characteristics startup and communication before the receiver is placed on the transmitter pad, the transmitter is in the standby state. in standby, the transmitter is waiting to detect any new, detectable object. once the receiver is placed on the pma transmitter pad, there are two states that the system must pass through before power transfer begins. these states are: digital ping, and identification and the final two states are: power transfer, and end-of-charge (eoc). figure 15. simplified pma-state machine. table 8. receiver power transfer operation. in standby, the transmitter is waiting to detect an object on its pad. once detected the tr ansmitter tries to initiate communication, emitting a predetermined signal called a ?digital ping?. if the receiver is aligned well enough to energize and if it responds in the correct manner, it is recognized by the transmitter as a pma capable device. at this point, if the identificati on state is not supported, the transmitter starts transmitting power to the receiver. if the identification state is supported, the receiver sends its unique rxid to the transmitter, which identifies it as a fully compliant pma device. after that transaction, the system enters the power transfer state and power transfer from the transmitter to receiver begins. the 5v ldo is enabled when the power transfer mode is initiated and the voltage at vrect, the output of the full- wave synchronous rectifier, is more than 5.6v. pma eoc a receiver that transmits a pma eoc signal shall remain in the power transfer phase but shall disable its output and shall continue to transmit pma eoc signals until the transmitter removes the power. the p9028ac operation is summarized in table 8 from the pma specification: description symbol value units maximum period in power transfer phase i out p9028ac product datasheet revision 1.0.3 21 ? 2015 integrated device technology, inc. applications information external components the p9028ac requires a minimum number of external components for proper operation, as indicated in figure 16, 17 and 18 as well as table 9, 10 and 11. ldo input capacitor (vrect capacitors) the ldo input capacitors (vrect capacitors) should be located as close as possible to the vrect pins, and ground (pgnd). ceramic capacitors are recommended for their lower esr and small profile. see figure 17 and table 10 for values and type of capacitor. vdd capacitor the p9028ac has an internal ldo regulator that must have a capacitor connected from the vdd pin to gnd. this capacitor should be as close as possible to the vdd pin with a close gnd connection. see figure 17, 18 and table 10, 11 for values and type of capacitor. output capacitor the output capacitor connection to the ground pin (pgnd) should be made as short as practical for maximum device performance. since the ldo has been designed to function with very low esr ca pacitors, a ceramic capacitor is recommended for best performance. for better transient response increase the total amount of output capacitance. for 1a load steps, an output capacitance of at least 10f is recommended. pcb layout considerations - for optimum device performance and lowest output phase noise, the following guidelines should be observed. please contact idt inc. for gerber files that contain the recommended board layout and application note an883, ?p9028ac layout guidelines?. - an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. signal tr aces not related to the p9028ac should be routed away from the ic as much as possible to avoid blocking thermal dissipation paths from the ic to the pcb. this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. - layout and pcb design have a significant influence on the power dissipation capabilities of power management ics because the surface mount packages used with these devices rely heavily on thermally conductive traces or pads to transfer heat away from the package. appropriate pc layout techniques should be used to remove the heat due to device power dissipation. - the following general guidelines will be helpful in designing a board layout for lowest thermal resistance: 1. pc board traces with large cross-sectional areas remove more heat. for optimum results, use large-area pcb patterns with wide copper traces, placed on the uppermost side of the pcb. 2. in cases where maximum heat dissipation is required, use double-sided copper planes connected with multiple vias. 3. thermal vias are needed to provide a thermal path to inner and/or bottom layers of the pcb to remove the heat generated by device power dissipation. power dissipation and thermal requirements the p9028ac is offered in a qfn-32 package which has a maximum power dissipation capability of about 1.9w and in a wlcsp package, the maximum power dissipation of which is determined by the number of thermal vias between the package and the printed circuit board. the maximum power dissipation of both packages is defined by the die?s specified maximum operating junction temperature, t j , of 125 c. the junction temperature rises when the heat generated by the device?s power dissipation goes through the package thermal resistance. the qfn package offers a typical thermal resistance, junction to ambient ( ja ), of 35 o c/w when the pcb layout and surrounding devices are optimized as described in the pcb layout considerations section. the wlcsp package has a typical ja of 70 o c/w with 7 thermal vias and 144 o c/w with no thermal vias. clearly, maximizing the thermal vias is highly recommended. the techniques as noted in the pcb layout section must be followed when designing the printed circuit board layout, as well as the placement of the p9028ac ic package in proximity to other heat-
p9028ac product datasheet revision 1.0.3 22 ? 2015 integrated device technology, inc. generating devices in a given application design. the ambient temperature around the power ic will also have an effect on the thermal limits of an application. the main factors influencing ja (in the order of decreasing influence) are pcb characteristics, die/package attach thermal pad size (qfn), thermal vias (wlcsp), and internal package construction. board designers should keep in mind that the package thermal metric ja is impacted by the characteristics of the pcb itself upon which the ic is mounted. for example, in a still-air environment, as is often the case, a significant amount of the heat generated (~85%) is absorbed by the pcb. changing the design or configuration of the pcb changes the overall thermal resistivity and, thus, the board?s heat- sinking efficiency. the use of integrated circuits in low-profile and fine-pitch surface-mount packages requires special attention to power dissipation. many system-dependant issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat- generating components, affect the power-dissipation limits of a given component. three basic approaches for enhancing thermal performance are listed below: 1. improving the power dissipation capability of the pcb design 2. improving the thermal coupling of the component to the pcb 3. introducing airflow into the system first, the maximum power dissipation for a given situation should be calculated: p d(max) = (t j(max) - t a )/ ja in which p d(max) = maximum power dissipation ja = package thermal resistance (c/w) t j(max) = maximum device junction temperature (c) t a = ambient temperature (c) the maximum recommended junction temperature (t j(max) ) for the p9028ac device is 125c. the thermal resistance of the 32-pin qfn package (nbg32) is nominally ja =35c/w. operation is specified to a maximum steady- state ambient temperature (t a ) of 85c. therefore, the maximum recommended power dissipation is: p d(max) = (125c - 85c) / 35c/w 1.14 watt. the thermal resistance for the wlcsp package (awg36) is nominally ja =70c/w with 7 thermal vias, the maximum recommended power dissipation is: p d(max) = (125c - 85c) / 70c/w 0.57 watt all the above-mentioned thermal resistances are the values found when the ics are mounted on a standard board of the dimensions and characteristics specified by the jedec 51 standard. thermal overload protection the p9028ac integrates thermal overload shutdown circuitry to prevent damage resulting from excessive thermal stress that may be encountered under fault conditions. this circuitry will shut down or reset the device if the die temperature exceeds 150c. to allow the maximum load current on each regulator and the synchronous rectifier, and to prevent thermal overload, it is important to ensure that the heat generated by the p9028ac is dissipated into the pcb. end of charge (eoc) in the event of thermal shutdown (150c), en, chg_end or teop pins assertion the device turns off the ldo and continually sends end of power (eop) packets in wpc or end of charge (eoc) in pma until the transmitter removes the power and the rectifier voltage on the receiver side drops below the uvlo threshold. nc pins that are indicated as ?not internally connected? should be soldered to the pcb ground plane to improve thermal performance with multiple vias exiting the bottom side of the pcb. this improves heat flow away from the package and minimizes package thermal gradients. dnc pins that are indicated as ?internally connected? must be left floating. special notes tqfn nbg32 package assembly note 1: unopened dry packaged parts have a one year shelf life. note 2: the hic indicator card for newly-opened dry packaged parts should be checked. if there is any moisture content, the parts must be baked for a minimum of 8 hours at 125 ? c within 24 hours of the assembly reflow process.
p9028ac product datasheet revision 1.0.3 23 ? 2015 integrated device technology, inc. p9028ac ac1 ac1 rect rect c rect pgnd1 stat r 1 agnd ac2 ac2 scl sda scl sda c s c d out out c out 5v ? output acm1 acm2 c mod1 c mod2 c clamp2 c clamp1 c bst1 c bst2 clamp2 bst2 bst1 clamp1 pgnd pgnd ilim r lim l rx fod1 r fod1 c 1 vdd clamp2 pgnd2 pgnd2 clamp1 fod2 r fod2 teop temperature ? control en chip ? enable charge ? complete chg_end/cs100 sns qfn only figure 16. simplified applications schematics. table 9. bill of materials. item quantity reference value 11l rx 7.5 ? h ? (custom ? coil) 1 22c mod1 , ? c mod2 100nf 32c clamp1 , ? c clamp2 470nf 42c bst1 , ? c bst2 10nf 52c out , ? c 1 10 ? f 61c rect 30 ? f 71c d 1800pf 82c s 400nf 9 1 led red_led 14 2 r fod1 , ? r fod2 tbd ? (sytem ? dependent) 15 1 r lim 30k 18 1 idtp9028ac idtp9028ac note 1 ? contact the factory for suitable coil recommendations.
p9028ac product datasheet revision 1.0.3 24 ? 2015 integrated device technology, inc. detailed system diagram wlcsp figure 17. p9028ac wlcsp applications schematic (see p9 028ac evaluation kit user manual for complete details).
p9028ac product datasheet revision 1.0.3 25 ? 2015 integrated device technology, inc. components selection wlcsp table 10. p9028ac wlcsp evaluation kit bill of materials. item quantity reference part ? number value pcb ? footprint 1 1 /en tp tp_25mil 2 2 c9,c16 c1005x7r1h103k050bb 10nf 402 3 2 c10,c15 umk105abj474kv \ f 0.47uf 402 4 6 c11,c12,c27,c28,c29,c42 grm155r61h104ke19d 0.1uf 402 5 9 c20,c21,c34,c35,c38,c39, grm155r61e475m 4.7uf 402 c43,c44,c45 6 2 c24,c32 c1005x5r1e105m050bc 1uf 402 7 1 c26 grm155r71h182ka01d 1.8nf 402 8 3 out1,gnd1,vrect 5015 1p test_pt_sm_135x70 9 2 r3,r4 tbd np 402 10 2 r5,r6 erj \ 1gef3002c 30k 201 11 2 r96,r97 erj \ 2gej472x 4.7k 402 12 1 u1 p9028ac idtp9028ac ? csp csp36p500x500 optional ? components 13 4 cs100,teop,stat,int tp tp_25mil 14 8 ac2,gnd3,gnd4,gnd5,gnd6, 28awg 28awg ac11,sda,scl 15 1 c41 grm155r61e475m np 402 16 4 gnd,fod1,gnd2,fod2, 5015 1p test_pt_sm_135x70 17 1 j1 sbh11 \ pbpc \ d07 \ st \ bk 14p p_014_2r 18 2 r1,r2 3223w \ 1 \ 504e 500k res_adj_smd_3p9x3p9 19 1 r82 erj \ 2ge0r00x 0 402 20 1 r85 rc0402jr \ 070rl 0 402
p9028ac product datasheet revision 1.0.3 26 ? 2015 integrated device technology, inc. detailed system diagram tqfn figure 18. p9028ac tqfn applications schematic (see p9028 ac evaluation kit user manual for complete details).
p9028ac product datasheet revision 1.0.3 27 ? 2015 integrated device technology, inc. components selection tqfn table 11. p9028ac tqfn evaluation kit bill of materials. item quantity reference part ? number value pcb ? footprint 1 3 /en,sda,scl tp tp_25mil 2 2 c9,c16 c1005x7r1h103k050bb 10nf 402 3 2 c10,c15 umk105abj474kv \ f 0.47uf 402 4 6 c11,c12,c27,c28,c29,c42 grm155r61h104ke19d 0.1uf 402 5 9 c20,c21,c34,c35,c38,c39, grm155r61e475m 4.7uf 402 c43,c44,c45 6 2 c24,c32 c1005x5r1e105m050bc 1uf 402 7 1 c26 grm155r71h182ka01d 1.8nf 402 8 3 out1,gnd1,vrect 5015 1p test_pt_sm_135x70 9 2 r3,r4 tbd np 402 10 2 r5,r6 erj \ 1gef3002c 30k 201 11 2 r96,r97 erj \ 2gej472x 4.7k 402 12 1 u1 p9028ac idtp9028ac ? qfn qfn_32ld_5x5_0p5mm optional ? components 13 4 cs100,teop,stat,int tp tp_25mil 14 6 ac2,gnd3,gnd4,gnd5,gnd6, 28awg 28awg ac11 15 1 c41 grm155r61e475m np 402 16 4 gnd,fod1,gnd2,fod2, 5015 1p test_pt_sm_135x70 17 1 j1 sbh11 \ pbpc \ d07 \ st \ bk 14p p_014_2r 18 2 r1,r2 3223w \ 1 \ 504e 500k res_adj_smd_3p9x3p9 19 1 r82 erj \ 2ge0r00x 0 402 20 1 r85 rc0402jr \ 070rl 0 402
p9028ac product datasheet revision 1.0.3 28 ? 2015 integrated device technology, inc. i 2 c register map the p9028ac has a one-time programmable i 2 c address that is set to default 0x25h. table 12. read registers - vrect voltage: vrect=5 x adc1<12:1> = [adc1<12:1>] x 5 x [1.8v/2 12 ]. byte ?? address ? byte ?? name ? bit ? field ? field ? name ? type ? default ? ? value ? description ? 0x40 reg0 7 a dc1<12> r vrect a dc code (average of 8 consecutive measurements) 0x40 reg0 6 a dc1<11> r vrect a dc code (average of 8 consecutive measurements) 0x40 reg0 5 a dc1<10> r vrect a dc code (average of 8 consecutive measurements) 0x40 reg0 4 a dc1<9> r vrect a dc code (average of 8 consecutive measurements) 0x40 reg0 3 a dc1<8> r vrect a dc code (average of 8 consecutive measurements) 0x40 reg0 2 a dc1<7> r vrect a dc code (average of 8 consecutive measurements) 0x40 reg0 1 a dc1<6> r vrect a dc code (average of 8 consecutive measurements) 0x40 reg0 0 a dc1<5> r vrect a dc code (average of 8 consecutive measurements) 0x41 reg1 7 a dc1<4> r vrect a dc code (average of 8 consecutive measurements) 0x41 reg1 6 a dc1<3> r vrect a dc code (average of 8 consecutive measurements) 0x41 reg1 5 a dc1<2> r vrect a dc code (average of 8 consecutive measurements) 0x41 reg1 4 a dc1<1> r vrect a dc code (average of 8 consecutive measurements) 0x41 reg1 3 reserved. r reserved. 0x41 reg1 2 reserved. r reserved. 0x41 reg1 1 reserved. r reserved. 0x41 reg1 0 reserved. r reserved.
p9028ac product datasheet revision 1.0.3 29 ? 2015 integrated device technology, inc. i 2 c register map (continued) table 13. read registers - iout current: i out is read directly from i out = adc2<12:1> = [adc1<12:1>] x [1.8a/2 12 ]. byte ?? address ? byte ?? name ? bit ? field ? field ? name ? type ? default ? ? value ? description ? 0x42 reg2 7 adc2<12> r iout adc code (average of 8 consecutive measurements) 0x42 reg2 6 adc2<11> r iout adc code (average of 8 consecutive measurements) 0x42 reg2 5 adc2<10> r iout adc code (average of 8 consecutive measurements) 0x42 reg2 4 adc2<9> r iout adc code (average of 8 consecutive measurements) 0x42 reg2 3 adc2<8> r iout adc code (average of 8 consecutive measurements) 0x42 reg2 2 adc2<7> r iout adc code (average of 8 consecutive measurements) 0x42 reg2 1 adc2<6> r iout adc code (average of 8 consecutive measurements) 0x42 reg2 0 adc2<5> r iout adc code (average of 8 consecutive measurements) 0x43 reg3 7 adc2<4> r iout adc code (average of 8 consecutive measurements) 0x43 reg3 6 adc2<3> r iout adc code (average of 8 consecutive measurements) 0x43 reg3 5 adc2<2> r iout adc code (average of 8 consecutive measurements) 0x43 reg3 4 adc2<1> r iout adc code (average of 8 consecutive measurements) 0x43 reg3 3 reserved. r reserved. 0x43 reg3 2 reserved. r reserved. 0x43 reg3 1 reserved. r reserved. 0x43 reg3 0 reserved. r reserved.
p9028ac product datasheet revision 1.0.3 30 ? 2015 integrated device technology, inc. i 2 c register map (continued) table 14. read registers - frequency: ? , where count is the decimal number represented by freq<10:1>. byte ?? address ? byte ?? name ? bit ? field ? field ? name ? type ? default ? ? value ? description ? 0x44 reg4 7 freq<10> r frequency value (10 bits). 0x44 reg4 6 freq<9> r frequency value (10 bits). 0x44 reg4 5 freq<8> r frequency value (10 bits). 0x44 reg4 4 freq<7> r frequency value (10 bits). 0x44 reg4 3 freq<6> r frequency value (10 bits). 0x44 reg4 2 freq<5> r frequency value (10 bits). 0x44 reg4 1 freq<4> r frequency value (10 bits). 0x44 reg4 0 freq<3> r frequency value (10 bits). 0x45 reg5 7 freq<2> r frequency value (10 bits). 0x45 reg5 6 freq<1> r frequency value (10 bits). 0x45 reg5 5 reserved. r reserved. 0x45 reg5 4 reserved. r reserved. 0x45 reg5 3 reserved. r reserved. 0x45 reg5 2 reserved. r reserved. 0x45 reg5 1 reserved. r reserved. 0x45 reg5 0 reserved. r reserved. ?
p9028ac product datasheet revision 1.0.3 31 ? 2015 integrated device technology, inc. i 2 c register map (continued) table 15. read registers ? miscellaneous functions. byte ?? address ? byte ?? name ? bit ? field ? field ? name ? type ? default ? ? value ? description ? 0x47 reg7 3 uvlo r 1: vrect is higher than uvlo threshold 0 : no meaning. 0x47 reg7 2 clamp_on r 0: vrect is lower than ac clamp threshold 1 : vrect is higher than ac clamp threshold 0x47 reg7 1 ldo_cl r 0: normal operation 1: ldo current limit exceeded. 0x47 reg7 0 reserved. r reserved. 0x48 reg8 7 charge_complete r 0: no meaning. 1: charge complete.. 0x48 reg8 6 reserved. r reserved. 0x48 reg8 5 reserved. r reserved. 0x48 reg8 4 reserved. r reserved. 0x48 reg8 3 reserved. r reserved. 0x48 reg8 2 reserved. r reserved. 0x48 reg8 1 die_temp r 0: die temperature < 150c 1: die temperature >150c 0x48 reg8 0 tx_type r 0: tx is wpc 1: tx is pma 0x54 reg20 [7:0] wpc_id_b0 r read otp26 content. 0x55 reg21 [7:0] wpc_id_b1 r read otp27 content. 0x56 reg22 [7:0] wpc_id_b2 r read otp28 content. 0x57 reg23 [7:0] wpc_id_b3 r read otp29 content. 0x58 reg24 [7:0] wpc_id_b4 r read otp30 content. 0x59 reg25 [7:0] wpc_id_b5 r read otp31 content. 0x5a reg26 [7:0] wpc_id_b6 r read otp32 content. 0x5b reg27 [7:0] pma_rxid_pre r read otp33 content. 0x5c reg28 [7:0] pma_rxid_msg r read otp34 content. 0x5d reg29 [7:0] pma_rxid_cer r read otp35 content. 0x5e reg30 [7:0] pma_rxid_b0 r read otp36 content. 0x5f reg31 [7:0] pma_rxid_b1 r read otp37 content. 0x60 reg32 [7:0] pma_rxid_b2 r read otp38 content. 0x61 reg33 [7:0] pma_rxid_b3 r read otp39 content. 0x62 reg34 [7:0] pma_rxid_b4 r read otp40 content. 0x63 reg35 [7:0] pma_rxid_b5 r read otp41 content. 0x64 reg36 [7:0] pma_rxid_crcb0 r read otp42 content. 0x65 reg37 [7:0] pma_rxid_crcb1 r read otp43 content.
p9028ac product datasheet revision 1.0.3 32 ? 2015 integrated device technology, inc. i 2 c register map (continued) table 16. read-write physical fod registers: see application note #814a. byte ?? address ? byte ?? name ? bit ? ? field ? field ? name ? type ? default ? ? value ? description ? 0x49 reg9 0-7 fod9<0-7> r/w 0 mcf correction for region 1 io1,io2,io3=000 0x4a reg10 0-7 fod10<0-7> r/w 0 bcf correction for region 1 io1,io2,io3=000 0x4b reg11 0-7 fod11<0-7> r/w 0 mcf correction for region 2 io1,io2,io3=010 0x4c reg12 0-7 fod12<0-7> r/w 0 bcf correction for region 2 io1,io2,io3=010 0x4d reg13 0-7 fod13<0-7> r/w 0 mcf correction for region 3 io1,io2,io3=100 0x4e reg14 0-7 fod14<0-7> r/w 0 bcf correction for region 3 io1,io2,io3=100 0x4f reg15 0-7 fod15<0-7> r/w 0 mcf correction for region 4 io1,io2,io3=110 0x50 reg16 0-7 fod16<0-7> r/w 0 bcf correction for region 4 io1,io2,io3=110 0x51 reg17 0-7 fod17<0-7> r/w 0 mcf correction for region 5 io1,io2,io3=111 0x52 reg18 0-7 fod18<0-7> r/w 0 bcf correction for region 5 io1,io2,io3=111 0x53 reg19 0-7 fod19<0-7> r/w 0 bcf correction for start-up phase ?
p9028ac product datasheet revision 1.0.3 33 ? 2015 integrated device technology, inc. package outline drawing wlcsp figure 19. wlcsp package outline drawing (awg36).
p9028ac product datasheet revision 1.0.3 34 ? 2015 integrated device technology, inc. landing pattern drawing wlcsp figure 20. wlcsp-36 landing pattern drawing ( awg36 ).
p9028ac product datasheet revision 1.0.3 35 ? 2015 integrated device technology, inc. package outline drawing tqfn figure 21. tqfn package outline drawing (nbg32).
p9028ac product datasheet revision 1.0.3 36 ? 2015 integrated device technology, inc. landing pattern drawing tqfn figure 22. qfn-40 5mmx5mm landing pattern drawing (nbg32).
p9028ac product datasheet revision 1.0.3 37 ? 2015 integrated device technology, inc. revision history revision changes 1.0.0 initial release 1.0.1 page 23: corrected teop pin name. page 41: removed ts pin register descriptions. 1.0.2 page 3: added note: for the wlcsp (awg36) package, connecting the 7 thermal balls to internal/external ground planes from top to bottom sides of the pcb, is recommended for improving the overall thermal performance. page 23: corrected part number p9028ac page 29: added information to the sentence. the thermal resistance for the wlcsp package (awg36) is nominally ja =70c/w with 7 thermal vias, the maximum recommended power dissipation is: 1.0.3 pages 24, 25, 26, 27: added 30k (r6) resistor from vrect pin to ground to schematic and bom. resistor is needed to pass pma3 certification, ping detection test. added tqfn schematic and bom.
p9028ac product datasheet revision 1.0.3 38 ? 2015 integrated device technology, inc. ordering guide table 17. ordering summary. idt part number part number marking package ambient temp. range shipping carrier p9028ac-x * p9028ac- xawgi8 p9028ac- xawgi wlcsp 36 0c to +85c tape and reel p9028ac-x * p9028ac-x * nbgi p9028ac-x * nbgi tqfn 32 0c to +85c tray p9028ac-x * p9028ac-x * nbgi8 p9028ac-x * nbgi8 tqfn 32 0c to +85c tape and reel *note ? this field is a custom value that is specific to each cu stomer. please contact your local sales team for your particula r value for this field. www.idt.com 6024 silver creek valley road san jose, california 95138 tel: 800-345-7015 disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to m odify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in cus tomer products. the informati on contained herein is provided without representation or warranty of any ki nd, whether express or implied, including, but not limited to, the suitability of i dt?s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s produc ts are not intended for use in life support systems or similar devices where the failure or m alfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express , written agreement by idt. integrated device technology, idt and the idt logo are register ed trademarks of idt. other tr ademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. ? copyright 2015. all rights reserved. ?

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